1. Field of the Invention
The present invention relates to a microprocessor. More specifically, the invention relates to a microprocessor which can perform data communication with a system resource having mutually different data ports.
2. Description of the Related Art
In a microprocessor which performs external data communication, it becomes necessary to use a bus common to various resources, such as memory and so forth, for communication.
However, bus widths of the resources are not always the same as that of the microprocessor. For instance, it may become necessary to connect a memory or I/O device having 8 bit width or 16 bit width to the microprocessor of 32 bits. () As an approach to this, there has been provided microprocessor having a bus sizing function dynamically adapting the bus width to that of the resources.
FIG. 5 shows an example of bus sizing operation, which has been disclosed in "MOTOROLA MC6800 User's Manual" P.7-6. The bus sizing operation will be briefly discussed on the basis of the disclosure in the above-identified Publication. It should be noted that, in FIG. 5, numbers shown with [] represent a bit number.
The reference numeral 500 denotes a register within a microprocessor, 501 denotes an aligner having the bus sizing function and 502 denotes an external data bus of the microprocessor. The reference numerals 503, 504 and 505 denote respective ports having the bit width of 32 bits, 16 bits and 8 bits, respectively. 510 to 513 denote unit data of 8 bits which are stored in the internal register 500.
Here, consideration is given for outputting of data from the register 500 to respective ports 503, 504 505.
To the port 503 having the bit width of 32 bits, the data 510 to 513 as the content of the internal register 500 can be transferred as they are.
For the port 504 having the bit width of 16 bits, the data 510 to 513 are separated into upper 16 bits 510 and 511 and lower 16 bits 512 and 513 and then transmitted sequentially.
For the port 505 having the bit width of 8 bits, the data 510 to 513 are divided into respectively 8 bit segments and transmitted sequentially.
In order to realize the above-mentioned operation, the aligner 501 which can control the width of the data bus and align the value of the internal register 500 per 8 bit unit segment, is provided.
FIG. 6 shows a layout of the microprocessor having the bus sizing function. The reference numeral 201 denotes a microprocessor, and 202 denotes a data path for performing actual operation. The data path 202 is provided the bit width of 32 bits. The data path 202 is connected to data bus interface circuits 300(0) to 300(31) which exchanges data with an external data bus via internal data bus 20(0) to 20(31). The data bus interface circuit 300(0) to 300(31) are connected to pads 400(0) to 400(31) for connecting with respective external data bus. Here, it should be noted that the number within [] represent the bit number. Also, the number within ( ) corresponds to the bit number.
As shown, the data bus interface circuit 300(0) to 300(31) and the pad 400(0) to 400(31) are arranged in alignment.
The microprocessor 201 is provided with an internal data bus of 32 bits for communication. On the other hand, the resource, such as the memory, the I/O interface or so forth, is assumed to have 8 bits and 16 bits other than 32 bit bus. In order to be dynamically adapted with the external resource, the data bus interface circuit 300(0) to 300(31) selects the internal data bus 20(1) to 20(31) in 4 ways of combination so that the data can be input and output from the pad 400(0) to 400(31). Accordingly, for each data bus interface circuit, four internal data buses are wired. Then, with a control signal, one of the internal data paths is selected for inputting to or outputting from among four internal data buses.
In the microprocessor 201 shown in FIG. 6, when the bus sizing per 8 bits unit, data communication is performed with the external resource via eight pads 400(0) to 400(7).
For instance, the pad 400(0) connected to the data bus interface 300(0) is connected to the internal data buses 20(0), 20(8), 20(16), 20(24). In case of the bus sizing per 16 bits unit, the internal data buses 20(0) and 20(16) are selected in order.
Similarly, the pad 400(1) connected to the data bus interface 300(1) is connected to the internal data buses 20(1), 20(9), 20(17) and 20(25). In case of the bus sizing per 16 bits unit, the internal data buses 20(1) and 20(17) are selected in order.
Accordingly, when the bus width of the external resource is 8 bits, in which the data input and output is performed in time division manner for four times by making the bus to correspond to [0} bit to {7} bit of the external data bus, internal data bus 20(0) to 20(7), 20(8) to 20(15), 20(16) to 20(23) and 20(24) to 20(31) are connected to the pad 400(0) to 400(7) in order.
On the other hand, when the bus width of the external resource is 16 bits, in which the data input and output is performed in time division manner for two times by making the bus to correspond to [0} bit to {15} bit of the external data bus, internal data bus 20(0) to 20(15) 20(16) to 20(31) are connected to the pad 400(0) to 400(15) in order.
Here, observing a destination of connection of the internal data bus 20(0), due to 8 bit bus sizing, the internal data bus 20(0) is connected to the data bus interface 300 at 0th bit, 8th bit, 16th bit and 24th bit arranged at 8 bits distance. With respect to other internal data buses, each of the internal data bus is connected to four bus interface circuits arranged at 8 bit distance, in similar manner.
In order to connect four data bus interface circuits distanced from each other to one internal data bus, it becomes a construction having a plurality of wiring on a layout of a chip in actual wiring of the internal data bus so as to make the wiring length large. Increasing of the wiring length causes increasing of the capacity of the wiring to expand inputting set-up period and outputting delay period. Furthermore, increasing of the wiring length inherently causes increasing of the chip area.